1. Field of Invention
The invention relates generally to memory interface systems, and more specifically to a method and apparatus for providing and arbitrating access to a shared memory by multiple devices, for applications such as multiprocessor systems and communications switching.
2. Description of the Related Art
Shared memories are used to facilitate data passing between multiple processes. A typical shared memory implementation involves the use of multiple ports. Each port may provide shared memory access to a different external device. The different devices, in turn, may be involved with the control or execution of different processes that pass the data.
In order to provide each port with access to the shared memory which is not significantly impacted by shared memory accesses by other ports, the path to the shared memory typically is designed with a bandwidth close to the sum of the bandwidths of the individual ports. This ensures that the data carrying capacity of the path is sufficiently large so that no port suffers a significant delay in accessing the shared memory even though multiple ports may seek access to the shared memory. Generally, this is achieved in one of two ways, or some combination thereof First, the shared memory access time may be designed to be much faster than the data transfer times for the individual ports. Second, the path width to the shared memory may be designed to be much greater than the path widths of the individual ports.
The first approach is to assign a time slot to each port during which data can be read from or written to the shared memory. For each port, the assigned time slot is shorter than the actual time required to transfer data through the port. Thus, the data is buffered temporarily during its transfer between a port and the shared memory. Ordinarily, the length of the port time slot is inversely proportional to the number of devices sharing access to the shared memory. A device using a particular port can gain access to the memory only during the assigned time slot for that port. Data is buffered between time slots. There have been shortcomings with this approach. For example, it often requires the memory access time to be significantly less than the port data transfer time. However, it is often impractical to have such a mismatch between data transfer rates for the ports and the shared memory.
The second approach also involves assigning a time slot to each port. For example, writes to the shared memory involve temporarily buffering multiple data words received at a respective port, and then providing them to the memory on a wide memory path all in one memory access cycle during the time slot designated for the port. Conversely, reads from the shared memory involve providing multiple words on the wide path all in one memory access cycle during a time slot designated for a respective port; temporarily buffering the words read from memory; and then transferring the words through the port. This second approach is particularly well suited to burst-mode systems in which data words are communicated in multi-word bursts through respective ports. A complete burst may be temporarily stored in a memory access buffer, and then may be written or read during a single memory access cycle through such a wide bandwidth path to the shared memory. By providing a path with an appropriately large bandwidth, each port may be made to appear to have exclusive access to the shared memory, unimpeded by data transfers through other ports.
The illustrative block diagram of FIG. 1 depicts an earlier implementation of a multi-port memory system in which k ports, each having word width m, equally share a common memory. Each burst includes k words. K memory access buffers each can store k m-bit words. Each buffer is connected to the shared memory by a k.times.m line wide path. The shared memory is k.times.m bits wide.
The illustrative drawings of FIG. 2 show a data format used in a typical multiport memory system such as that in FIG. 1. During a transfer of data into the shared memory, a k word burst of m-bit words passes through a port. The entire burst is briefly stored in a single memory access buffer. Then, during a prescribed time slot, all k-words of the burst are simultaneously transferred from the buffer and written to the shared memory on the k.times.m path. During a transfer of data out of the shared memory, k words are read from the shared memory during another prescribed time slot and are transferred to a single memory access buffer. Then the buffered data is transferred through the port associated with that buffer.
The port which originally inputted the burst may be different from the port that outputs the burst. The shared memory temporarily stores the burst so that it can be routed from the input port to the output port. Thus, the system of FIG. 1 can be used to pass data between ports.
More specifically, for example, in a memory write operation, k m-bit words received through a respective port are buffered by a memory access buffer assigned to that port. Subsequently, during a time slot reserved for that memory access buffer, all of the k m-bit words stored in the assigned buffer are simultaneously written to the shared memory on the shared k.times.m-bit wide path. In a like manner, each of the other buffers can store k m-bit words on behalf of their own associated ports. The entire contents (all k words) of each individual buffer can be written to the shared memory during the individual time slot reserved for that buffer. A memory read operation is analogous, with the steps of the write operation reversed.
A disadvantage of this prior implementation is the large number of interconnection pins between a buffer and the bus in a large multi-port system. FIG. 3 is a block diagram depicting another conventional multi-port shared memory system. The data format used involves 16 word bursts of 72 bits per word (64-bit data plus 8-bit parity). The shared memory bus has a width of 1152 lines (16 words.times.72 bits/word). The bus is connected to each of 16 memory access buffers. Each buffer would need more than 1224 data pins, 1152 to connect to the bus and 72 to connect to the port. Unfortunately, the 1152 data pins connected to the bus would each require high drive capability to operate on a bus connected to all 16 buffers and to the shared memory. FIG. 3 shows an illustrative bus capacitance that must be overcome by the buffer pins.
Thus, there has been a need for an improved architecture for providing multiple port access to a shared memory. The architecture should require fewer pins for memory access buffers and should not require high drive capability for buffer pins. The present invention meets those needs.